A processor often comprises a translation lookaside buffer (TLB), which is used to implement virtual memory. The TLB typically operates as a cache for a plurality of “translation pairs,” wherein each translation pair maps or translates a virtual address to a physical address. Because the translation from a virtual address to a physical address often involves large complex data structures that a processor would be unable to efficiently store, a TLB is used to store the most recently accessed translation pairs for quick use by the processor.
Generally, control logic of the processor presents a virtual address to a memory management unit (MMU), which is often located on the processor. The MMU refers to a logical unit that manages access to a defined address space such as, for example, the virtual address space defined for a system implementing a virtual memory architecture. The MMU first searches the TLB for the translation pair related to the virtual address presented. If the virtual address is not found in the TLB, then the processor accesses a page table, which is usually stored in random access memory (RAM), located external to the processor, to bring the translation into the TLB. A page table generally refers to a data structure that provides a map between virtual addresses and physical addresses. The page table is normally indexed by page number and contains information on where the page is located within a memory hierarchy (e.g. disk, main memory, etc.).
The TLB typically holds a limited number of translation pairs. Consequently, as the MMU inserts translation pairs into the TLB, it also periodically removes translation pairs to make room for new translation pairs. The removal of translation pairs can be done randomly, or it can be based upon some logical algorithm. For example, the least used translation pair may be removed first. The TLB can also hold other information from the page table, which may be desirable to manage access to the pages referenced by a given translation pair.
Further, if a system change renders a TLB translation pair inaccurate, then the inaccurate translation pair is often explicitly purged so that the processor will not attempt to access memory based on the inaccurate translation pair. For example, the page table may be updated, thereby making a translation that is currently stored in the TLB obsolete. This translation pair may be purged from the TLB in response to the page table update.
In a multiprocessor system, a global page table is often used to manage RAM, and each processor has its own TLB, which stores translation pairs related to processes owned by each processor in the system. In this regard, if a system change occurs that modifies the page table, then the operating system transmits a purge signal to each of the processors in the multiprocessor system, so that if a processor's TLB contains a translation pair related to the modification in the page table, then the processor can purge the TLB translation pair and purge any mini-TLBs or instruction queues that may attempt to use data related to the deleted address.
At times, a processor can become so busy responding to purge signals transmitted by the operating system that “starvation” occurs. Starvation is a term used to describe unproductive operation of a processor when it is unable to proceed with subsequent instructions due to the lack of usable resources.